1. Field of Invention
This invention relates to a semiconductor process and a product thereof, and particularly relates to a method for fabricating a semiconductor device, and to a semiconductor device and a structure of a semiconductor layer made by the method.
2. Description of Related Art
A FinFET typically includes a semiconductor fin, a gate crossing over the fin to form a tri-gate structure, and a source and a drain beside the portion of the fin under the gate. In a strained silicon process applied to FinFET, the portions of the fin not under the gate are recessed after the gate is formed, and a semiconductor compound having a lattice parameter different from that of the material of the fin is grown based on the recessed portions of the fin to serve as a source and a drain.
Because the fin structure usually protrudes from the isolation layer, the top of the recessed fin is near the isolation layer, so the semiconductor compound layer easily touches the isolation layer and becomes asymmetric.
Moreover, when the semiconductor compound layer includes silicon-phosphorus (SiP) and SiP is deposited in the epitaxy process, many dislocations in <111> direction occur due to competition of phosphorus and chlorine in the epitaxy process. Hence, there is concern on issues of device degradation, drain-induced barrier lowering (DIBL), self-aligned contact (SAC) and so on.